Re: gcc-3.1.1 on alpha

[Bill Allombert <allomber@math.u-bordeaux.fr>]

On Mon, Sep 23, 2002 at 08:16:51PM +0200, Bill Allombert wrote:
> On Tue, Jul 30, 2002 at 06:00:55PM -0400, Igor Schein wrote:
> > Hi,
> > 
> > gcc-3.1.1 miscompiles latest CVS pari code on alpha-linux:
> > 
> > ? conjvec(Mod(x^2+x+1,x^3-x-1))
> >   ***   bug in GP (Floating Point Exception), please report
> > 
> > That's with debugging binary + alpha kernel.  With generic kernel it
> > works fine. 

It looks like mulll is not specified correctly. It allowed gcc
to use the same register in input and ouput, clobbering it.
I have no knowledge of the alpha asm, so I do not really know
if I do something meaningful.  Here a patch that fix all the asm macros.

Please test!!

Cheers,
Bill.

Index: src/kernel/alpha/asm0.h
===================================================================
RCS file: /home/megrez/cvsroot/pari/src/kernel/alpha/asm0.h,v
retrieving revision 1.3
diff -u -r1.3 asm0.h
--- src/kernel/alpha/asm0.h	2001/10/12 20:27:09	1.3
+++ src/kernel/alpha/asm0.h	2002/09/24 15:53:57
@@ -38,8 +38,8 @@
 
 #define addll(a, b)\
 ({ register ulong __value, __arg1 = (a), __arg2 = (b); \
-  __asm__ volatile ("addq %2,%3,%0\n\tcmpult %4,%2,%1" \
-   : "=r" (__value), "=r" (overflow) \
+  __asm__ ("addq %2,%3,%0\n\tcmpult %4,%2,%1" \
+   : "=&r" (__value), "=r" (overflow) \
    : "r" (__arg1), "r" (__arg2), "0" ((ulong) 0)); \
   __value; \
 })
@@ -47,55 +47,55 @@
 #define addllx(a, b)\
 ({ register ulong __value, __arg1 = (a), __arg2 = (b), __temp; \
  __asm__ volatile ("addq %3,%4,%0\n\tcmpult %5,%3,%2\n\taddq %5,%6,%0\n\tcmpult %5,%6,%1\n\taddq %6,%7,%1\n\t" \
-   : "=r" (__value), "=r" (overflow), "=r" (__temp) \
+   : "=&r" (__value), "=r" (overflow), "=r" (__temp) \
    : "r" (__arg1), "r" (__arg2), "0" ((ulong) 0), "1" (overflow), "2" ((ulong) 0)); \
 __value; \
 })
 
 #define subll(a, b)\
 ({ register ulong __value, __arg1 = (a), __arg2 = (b); \
-  __asm__ volatile ("subq %2,%3,%0\n\tcmpult %2,%4,%1" \
-   : "=r" (__value), "=r" (overflow) \
+  __asm__ ("subq %2,%3,%0\n\tcmpult %2,%4,%1" \
+   : "=&r" (__value), "=r" (overflow) \
    : "r" (__arg1), "r" (__arg2), "0" ((ulong)0)); \
   __value; \
 })
 
 #define subllx(a, b)\
 ({ register ulong __value, __arg1 = (a), __arg2 = (b), __temp1, __temp2; \
-__asm__ volatile ("subq %4,%5,%2\n\tcmpult %4,%8,%3\n\tsubq %8,%7,%0\n\tcmpult %8,%6,%1\n\taddq %7,%9,%1\n\t" \
-   : "=r" (__value), "=r" (overflow), "=r" (__temp1), "=r" (__temp2)  \
+__asm__ ("subq %4,%5,%2\n\tcmpult %4,%8,%3\n\tsubq %8,%7,%0\n\tcmpult %8,%6,%1\n\taddq %7,%9,%1\n\t" \
+   : "=r" (__value), "=r" (overflow), "=&r" (__temp1), "=r" (__temp2)  \
    : "r" (__arg1), "r" (__arg2), "0" ((ulong)0), "1" (overflow), "2" ((ulong)0), "3" ((ulong)0)); \
  __value; \
 })
 
 #define shiftl(a, b) \
 ({ register ulong __value, __arg1 = (a), __arg2 = (b), __temp; \
- __asm__ volatile ("subq %5,%4,%2\n\tsll %3,%4,%0\n\tsrl %3,%6,%1\n\t" \
-   : "=r" (__value), "=r" (hiremainder), "=r" (__temp) \
+ __asm__ ("subq %5,%4,%2\n\tsll %3,%4,%0\n\tsrl %3,%6,%1\n\t" \
+   : "=r" (__value), "=r" (hiremainder), "=&r" (__temp) \
    : "r" (__arg1), "r" (__arg2), "n" ((ulong) 64), "2" ((ulong)0)); \
  __value; \
 })
 
 #define shiftlr(a, b) \
 ({ register ulong __value, __arg1 = (a), __arg2 = (b), __temp; \
- __asm__ volatile ("subq %5,%4,%2\n\tsrl %3,%4,%0\n\tsll %3,%6,%1\n\t" \
-   : "=r" (__value), "=r" (hiremainder), "=r" (__temp) \
+ __asm__ ("subq %5,%4,%2\n\tsrl %3,%4,%0\n\tsll %3,%6,%1\n\t" \
+   : "=r" (__value), "=r" (hiremainder), "=&r" (__temp) \
    : "r" (__arg1), "r" (__arg2), "n" ((ulong) 64), "2" ((ulong)0)); \
  __value; \
 })
 
 #define mulll(a, b) \
 ({ register ulong __value, __arg1 = (a), __arg2 = (b); \
- __asm__ volatile ("umulh %2,%3,%1\n\tmulq %2,%3,%0\n\t" \
-   : "=r" (__value), "=r" (hiremainder) \
+ __asm__ ("umulh %2,%3,%1\n\tmulq %2,%3,%0\n\t" \
+   : "=r" (__value), "=&r" (hiremainder) \
    : "r" (__arg1), "r" (__arg2)); \
  __value; \
 })
 
 #define addmul(a, b) \
 ({ register ulong __value, __arg1 = (a), __arg2 = (b), __temp; \
- __asm__ volatile ("mulq %3,%4,%0\n\tumulh %3,%4,%2\n\taddq %5,%6,%0\n\tcmpult %5,%6,%1\n\taddq %7,%6,%1\n\t" \
-   : "=r" (__value), "=r" (hiremainder), "=r" (__temp) \
+ __asm__ ("mulq %3,%4,%0\n\tumulh %3,%4,%2\n\taddq %5,%6,%0\n\tcmpult %5,%6,%1\n\taddq %7,%6,%1\n\t" \
+   : "=&r" (__value), "=r" (hiremainder), "=r" (__temp) \
    : "r" (__arg1), "r" (__arg2), "0" ((ulong) 0), "1" (hiremainder), "2" ((ulong) 0)); \
  __value; \
 })