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Bill Allombert on Thu, 05 Jan 2023 11:05:46 +0100
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Riscv-V/64 assembly kernel
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- To: pari-dev@pari.math.u-bordeaux.fr
- Subject: Riscv-V/64 assembly kernel
- From: Bill Allombert <Bill.Allombert@math.u-bordeaux.fr>
- Date: Thu, 5 Jan 2023 11:04:39 +0100
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Dear PARI developers,
I have added a assembly level-0 kernel for Risc-V/64.
I suppose it should work with Risc-V/32 but I do not have a system to test it.
Unfortunately, it seems the Risc-V/64 ISA was not designed with multiprecision in
mind (it seems a copycat of the 30-years-old DEC alpha ISA).
Cheers,
Bill.